In semiconductor devices, input receivers are widely used to receive input signals from outside of the devices. With recent increases in the operation speed of semiconductor devices, there is a need to increase the sensing speed of input receivers. In the field of memory devices, as data transfer speeds increase, a double data rate (DDR) semiconductor memory device has been developed. The DDR semiconductor memory device employs a rising edge and a falling edge of a clock signal to process data so as to increase the operation speed of devices.
FIG. 1 is a circuit diagram illustrating an input receiver 10 used in a DDR semiconductor memory device. Referring to FIG. 1, the input receiver 10 comprises a pre-amplifier 12, a sense amplifier 14, and a latch circuit 16. The pre-amplifier 12 amplifies an input signal IN, from outside of the memory device, with reference to a reference voltage VREF. The pre-amplifier 12 typically comprises a differential pair of PMOS transistors for receiving input signals. The sense amplifier 14 amplifies an output signal OUT1 and an inverted output signal OUT2 of the pre-amplifier 12 in response to a rising edge of a clock signal CLK. The latch circuit 16 latches an output signal OUT3 and an inverted output signal OUT4 of the sense amplifier 14 so as to generate a final output signal OUT and an inverted final output signal OUTB to other circuits in the DDR semiconductor memory device.
Currently, DDR semiconductor memory devices are divided into three types: DDR1, DDR2, and DDR3, with maximum operating frequencies of 400 MHz, 800 MHz, and 1.6 GHz, respectively. As the operation frequencies of memory devices increase from generation to generation, the prior art input receiver cannot respond immediately, and the output signal OUT and the inverted final output signal OUTB may have a skewed phenomenon as shown in FIG. 2. One consequence of the skew is that the signals OUT and OUTB do not cross the midpoint VMID at the same time. Instead, the midpoint crossings are offset by a skew time Td, which is typically on the order of 50 picoseconds or more. Such skew times are unacceptable for optimal differential signal processing, particularly with high speed applications.
Therefore, there is a need to provide a multi-stage receiver that exhibits low skew for high speed applications.